1. Field of the Invention
This invention generally relates to a circuit and method for gain control, and in particular to a circuit and method for gain control in wireless or wired communication systems.
2. Background of the Related Art
FIG. 1 illustrates a wireless receiver conceptually divided into two major sections being an analog front-end and a base-band digital signal processor (DSP). As shown in FIG. 1, in a receiver 100 an analog front-end 106 receives a modulated signal through an antenna 102, amplifies the modulated signal and down-converts the modulated signal directly to a low frequency 108 or through a suitable intermediate frequency (IF). The low frequency analog signal 108 is converted to digital bits by an analog-to-digital converter and goes to the base-band DSP section 110 for demodulation and further digital processing. An output 112 of the DSP section 110 is received by a user.
The analog front-end generally needs good sensitivity to detect the desired signal despite a weak signal strength and a linearity. Among different types of architectures used in radio frequency integrated circuits (RF ICs), the direct conversion architecture, also known as homo-dyne, has advantages for low-power applications.
FIG. 2 shows a block diagram of a related art direct conversion receiver 200. The direct conversion receiver 200 is important because it can accomplish channel selection filtering by processing within a chip, which helps to reduce the number of off-chip components, and thereby achieve better miniaturization. As shown in FIG. 2, the related art direct conversion receiver 200 is a highly integrated receiver that includes an antenna 202 that is connected to a low noise amplifier (LNA) 210 through a duplex filter 206. The LNA 210 has an output 212 that is respectively fed into a first mixer 216 and a second mixer 218. A serial programming interface 220 receives an input 223 from outside the direct conversion receiver 200, and also receives an output 229 from a crystal oscillator 227. The serial programming interface 220 outputs a channel setting 224 to a frequency synthesizer 228. A clock generator 222 also receives an input 225 from the crystal oscillator 227 and outputs a reference clock 226 to the frequency synthesizer 228. The frequency synthesizer 228 is made up of a PFD 232, a loop filter 230, a prescaler 234, and a voltage-controlled oscillator (VCO) 236. An output 240 of the frequency synthesizer 228 is received by a phase shifter 244. The phase shifter 244 has a +45xc2x0 output 246 fed into the mixer 216 and a xe2x88x9245xc2x0 output 248 fed into the second mixer 218.
In the related art direct conversion system 200, a desired RF signal passing the duplex filter 206 and amplified by the LNA 210 is directly down converted by the mixer 216 because a local oscillator (LO) frequency 246, which is the phase shifted signal 240 from the frequency synthesizer 228, is equal to a carrier frequency of the desired RF signal. The down converted signal 250 is amplified by the variable gain amplifier (VGA) 252 before the base band (BB) filter 256 to get the amplitude large enough to overcome the large noise floor of the BB low pass filter 256 before the analog-to-digital converter (ADC) 260, which outputs one channel 280 (e.g., in-phase channel I) of the direct conversion receiver 200. A mixer 218, a VGA 266, a BB filter 270 and an ADC 274 operate to output a second channel 276 (e.g., quadrature-phase channel Q) of the direct conversion receiver 200.
The simplicity of the direct conversion architecture offers two important advantages over superheterodyne architecture. First, the problem of generation of images is circumvented because an intermediate frequency (IF) in the superheterodyne receiver is baseband (i.e., FIF=0) in the direct conversion receiver. As a result, no image filter is required and the LNAs do not have to drive a 50-ohm load. Second, the IF SAW filter and subsequent down-conversion stages can be replaced with low-pass filters and baseband amplifiers, both of which can be easily implemented in a single chip.
However, the related art direct conversion receivers have disadvantages for high performance radio receivers. First, rejection of out-of-channel interferers with an active low-pass filter is more difficult than with a passive filter because active filters exhibit much more severe noise-linearity-power trade-offs than do their passive filter counterparts. However, several related art topological candidates for baseband circuits will now be described.
As shown in FIG. 3, an input 302 for a related art baseband circuit 300a is then transmitted to a low-pass BB filter 304 that suppresses out-of-channel interferers, thereby allowing a series connected amplifier 308 to be a nonlinear, high-gain VGA amplifier. The low-pass filter 304 further allows an ADC 312 to have a moderate dynamic range. However, the low-pass filter 304 preceding the amplifying stages imposes tight noise-linearity trade-offs in the baseband circuit 300a. An output 314 of the ADC 312 is the output of the baseband structure.
As shown in FIG. 3, a second related art baseband circuit 300b relaxes the LPF noise requirements while demanding a higher performance in the amplifier. In the baseband circuit 300b, an input 316 is initially fed into a VGA 318, and an amplified signal 320 of the VGA 318 is received by a low-pass BB filter 322. An output 324 of the BB filter 322 is received by an ADC 326. The ADC 326 has an output 328 that is the output of the second baseband structure.
As shown in FIG. 3, a third related art baseband circuit 300c demonstrates the use of channel filtering in the digital domain. In the baseband circuit 300c, an input 330 is fed into a VGA 332, and an output 334 of the VGA 332 is received by an ADC 336. A BB filter 340 receives an output 338 of the ADC 336. An output 342 of the BB filter 340 is the output of the third baseband circuit 300c. In the third baseband circuit 300c, the ADC 336 must achieve both a high degree of linearity so as to digitize the signal with minimal intermodulation of interferers, as well as exhibit a thermal and quantization noise floor well below the signal level.
As described above, trade-offs required by the individual baseband structures shown in FIG. 3 are alleviated by combining the above methods, so that amplification and filtering are distributed to several gain and filter stages, which optimizes the performance. In modern communication systems, the required channel filtering must exceed 60 dB in order to reject interferers in nearby channels. Also, the required signal gain must exceed 70 dB. The implementation of baseband circuits without external passive elements are quite difficult, regardless of any configuration shown in FIG. 3, because the front-end stage has too severe dynamic range requirements. However, the dynamic range requirements of individual elements of a baseband circuit can be relaxed by employing several gain and filtering stages in series.
FIG. 4 is a block diagram that shows a related art direct conversion receiver. As shown in FIG. 4, a direct conversion receiver 400 includes a baseband circuit 420 with a plurality of amplifiers and filters. However, the specific configuration of the baseband circuit 420 can be modified depending on system requirements.
As shown in FIG. 4, an RF signal is received by an antenna 402 and filtered by a duplex filter 406, and a filtered signal 408 is amplified by a LNA 410. The filtered amplified signal 412 is down converted to a baseband signal by a local oscillator (LO) signal 416 in a mixer 414. Within the baseband circuit 420, an output 418 from the mixer is variously amplified and filtered before being output to an ADC 442. As shown in FIG. 4, the baseband circuit 420 uses a first VGA 422, a first BB filter 426, a second VGA 430, a second BB filter 434, and a third VGA 438 connected in series between the mixer 414 and the ADC 442, which produces an output 444 of the front end of the direct conversion receiver 400.
The related art communication 400 receiver implements a dedicated gain-control scheme in the baseband circuit 420 to give best performance during demodulation. Especially for a CDMA system, automatic gain control loops have critical importance in determining system performance. However, the complex baseband circuit shown in FIG. 4 has various disadvantages. When the distributed filtering scheme is incorporated as shown in FIG. 4, the gain control becomes difficult because the total gain should also be distributed between several gain stages while currently considering interference levels.
FIGS. 5A and 5B are diagrams that illustrate variable system performance of the complex baseband circuit 420 within the direct conversion receiver 400. Every gain and filtering stage in the direct conversion receiver has limits to its maximum and minimum signal level, namely every gain and filtering stage has a limited dynamic range. The signal level in any stage should lie within the dynamic range of that stage.
FIG. 5A shows signal propagation diagram 503 for the case where the signal level lies within the bound. As shown in FIG. 5A, in the signal propagation diagram 503, the system 400 has a maximum limit 510. A desired signal 546, which is less than an interferer output 548, when received and measured at the output of the antenna 402. At the output 412 of the LNA 410, the desired signal level 550 increases, however, the interferer level 552 also increases and remains larger than the signal level 550. The desired signal level 554 is increased at the output of the first VGA 422, but the interferer level 556 is increased and remains larger than the desired signal level 554. At the output of the second VGA 430, the signal level 558 is larger than the interferer level 560. At the output 440 of the third VGA 438, the signal level 562 is at is at a required output level 515 for input to the ADC 442 while the interferer level 564 is significantly reduced compared to the desired signal level 562.
On the other hand, FIG. 5B shows signal propagation diagram 505 for a case where the gain distribution is not proper. As shown in FIG. 5B, in the Problem) signal propagation diagram 505, the system 400 has a maximum limit of signal level 520. A desired signal level 572 is less than an interferer signal level 574 when received and measured at the output of the antenna 402. At the output 412 of the LNA 410, the signal level 576 increases, however, the interferer level 578 also increases and remains larger than the desired signal level 576. The desired signal level 580 is increased at the output of the first VGA 422, but the interferer level 582 is increased and remains larger than the signal level 580. Further, the interferer level 582 is above the maximum limit of signal level 520 causing a linearity problem 530. At the output of the second VGA 430, the signal level 584 is larger than the interferer level 586. At the output 440 of the third VGA 438, the signal level 588 is at a required signal level 525 for input to the ADC 442, while the interferer level 592 is significantly reduced compared to the signal level 588. The total gain in both cases as shown in FIGS. 5A and 5B is the same, but the system 400 performance will be severely degraded for the situation shown in FIG. 5B.
FIG. 6 is a block diagram that shows a related art superheterodyne receiver. As shown in FIG. 6, a superheterodyne receiver 600 includes an antenna 602, which has an output 604 fed into a duplex filter 606, and an output 608 of the duplex filter 606 is received by the LNA 610. An output 612 of the LNA 610 is received by an image rejection filter 614 and an output 616 of the image rejection filter 614 is received with an LO signal 620 by the mixer 618. An output 622 of the mixer 618 is received by a SAW filter 624. An output 626 of the SAW filter 624 is fed into a second VGA 628 whose output 630 is received by an integrated BB filter 632. An output 634 of the integrated BB filter 632 is received by an ADC 636.
The related art superheterodyne receiver 600 with AGC functionality uses the IF SAW filter 624 to reduce the interferers to negligible levels compared to desired signal levels. Moreover, an external SAW filter has no limit on its dynamic range, and therefore it can filter out large interferences without intermodulation. This is the primary reason communication receivers use such a configuration. In the related art superheterodyne receiver 600, gain control is quite simple as shown in FIG. 7.
FIG. 7 is a diagram that illustrates gain by stages of the superheterodyne receiver 600. As shown in the signal propagation diagram 705, the superheterodyne receiver 600 has a maximum limit of signal level 710. In the case illustrated in FIG. 7, an interference level 742 is greater than a desired signal level 740 when outputted by the antenna 602. After the LNA 610, the desired signal level 744 has increased, but remains less than the interferer level 746. After the mixer 618, the desired signal level 748 has increased and the interferer level 750 has also increased and remains larger than the desired signal level 748. At the output 626 of the SAW filter 624, the desired signal level 752 is stronger than the interferer level 754. After the VGA 628, the desired signal level 756 is increased while the interferer level 758 remains at the same level as the interference level 754. Prior to input to the ADC 636, the desired signal level 760 is at a required signal level 715 while the interferer level 762 is reduced compared to the signal level 760.
In the related art superheterodyne receiver, when the desired signal level is small enough to lie within the ADC""s full dynamic range, the baseband modem sends a new signal indicating an increase in gain. When the desired signal level is large, the baseband modem reduces the gain so as not to overload the ADC.
As described above, the related art receivers have various disadvantages. When the distributed gain is incorporated in the related art receivers, gain control should be distributed between several gain stages and distributed while considering interface levels. However, in the related art receivers each gain stage corrects its gain by itself, the total gain loop can become unstable because multiple feedback loops arise during gain control.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a receiver and method of operating same that substantially obviates at least one of the disadvantages of the related art.
Another object of the present invention is to provide automatic gain control in a wired or wireless receiver in which channel selection filtering and gain assignment is distributed to several gain and filtering stages.
Another object of the present invention is to provide a gain control circuit that monitors internal signal levels of the receiver and reflects those monitored levels in the gain control.
Another object of the present invention is to provide a receiver with separate gain stages and method of operating same in which a baseband modem generates the actual gain control.
Another object of the present invention is to provide a radio frequency receiver with separate gain stages and a gain control circuit adjusts the gain by gain stages in order to reduce stability problems and linearity problems.
Another object of the present invention is to provide a radio receiver and method of operating that provides gain control by receiving detection readings from each of the gain stages and modifying distributed gain amounts to control total gain within the receiver to provide a stable and robust gain control method to achieve increased linearity and increased performance relative to noise.
Another object of the present invention is to provide a radio receiver and method of operating that reduces gain control problems for highly integrated radio receivers by providing sufficient prior information about the signal level of each internal stage to a baseband modem or the receiver itself.
Another object of the present invention is to provide a radio receiver and method of operating that provides automatic gain control that controls all gain stages from a low noise amplifier to amplifiers after the analog-to-digital conversion.
Another object of the present invention is to provide an automatic gain control device for a highly integrated radio receiver that controls all gain control stages from an initial amplifier to post amplifiers after the analog-to-digital converter to increase system performance without degrading linearity and stability.
Another object of the present invention is to provide a reliable high speed, low noise, single chip CMOS RF communication system and method for using same.
Another object of the present invention is to provide a CMOS RF receiver on a single chip using multiple gain control stages in the receiver and baseband structure that are centrally controlled to meet desired gain for a selected RF channel.
To achieve at least the above objects and advantages in whole or in part, and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a direct conversion communication system that includes a first gain stage that amplifies selected signals among received signals having a carrier frequency, a demodulation-mixer that mixes the received amplified carrier frequency selected signals and outputs baseband selected signals, a baseband amplification circuit that includes a plurality of gain stages that receive the baseband selected signals and selectively amplify in-channel signals to a prescribed amplitude, and a gain controller coupled to receive outputs of the gain stages and to control each of the gain stages, wherein the gain controller controls distributed gain among the gain stages to achieve a prescribed total gain.
To further achieve at least the above objects and advantages in whole or in part, and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a method of operating a communication system that includes receiving signals including selected signals having a carrier frequency, first amplifying the received selected signals, detecting a first output level of the first amplified selected signals, mixing the first amplified selected signals to output demodulated selected signals having a frequency reduced from the carrier frequency, second amplifying the demodulated selected signals until the selected signals reach a prescribed criteria, wherein the second amplifying includes sequentially amplifying the selected signals, detecting a second output level of the second amplified selected signals, digitizing the second amplified selected signals, determining an amplification amount of the digitized selected signals and generating a gain control signal responsive thereto, and controlling a gain distributed among the first and second amplifying according to the gain control signal and the first and second output levels.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.